1. Technical Field of the Invention
This invention relates generally to controlling operating conditions such as clock frequency and supply voltage set point of a circuit, and more specifically to doing so as a function of the operating temperature and instantaneous voltage of the circuit.
2. Background Art
FIG. 1 illustrates a prior art system 10 in which a power supply 12 provides electricity to a voltage regulator 14, which in turn provides an operating voltage Vcc to a load circuit 16. The load circuit (or some other entity, not shown) provides a voltage identification control signal VID to the voltage regulator to tell the voltage regulator what operating voltage it should output to the load circuit. Regardless of the requested voltage specified by the voltage identification control signal, the actual instantaneous voltage seen at the load will typically vary over time, as the current consumed varies depending upon what the load is doing at the moment. This is due, in part, to changes in voltage drop seen across resistance in the line between the voltage regulator and the load.
FIG. 2 illustrates a prior art system 20 in which a power supply 12 provides electricity to a voltage supply which provides an operating voltage Vcc to a clock generator 22 (and to other elements of the system including the load). In some cases, the clock generator can be part of the load circuit. The clock generator provides a clock signal CLK to the load circuit 16. A thermal diode 24 or other suitable device determines the operating temperature of the load circuit, and provides a temperature signal T to a thermal throttling mechanism 26. According to the prior art, if the load circuit is too hot, the thermal throttling mechanism sends a frequency control signal F to the clock generator, causing the clock generator to generate a lower-frequency clock signal. At this lower frequency, the load circuit will operate at a lower temperature. Once the load circuit is cool enough, the thermal throttling mechanism can alter the frequency control signal to enable the clock generator to raise the clock frequency, improving performance of the load circuit. According to the more recent prior art, the thermal throttling mechanism also sends a signal (such as a VID signal) to the voltage regulator, to alter the operating voltage of the load.
FIG. 3 illustrates a prior art system 30 in which the power supply 12 provides power to the voltage regulator 14 which powers a clock generator 22 (and other elements including the load circuit), which in turn provides the clock signal CLK to the load circuit 16. The clock generator can, in some embodiments, be constructed as part of the load circuit. A power manager 32 receives a power supply signal G/B from the power supply indicating whether the system is running on grid power (G) or on battery power (B). In response to the state of the power supply signal, the power manager sends a frequency control signal F to the clock generator. When the system is running on grid power, the clock generator will generate a high-frequency clock signal to maximize performance of the load circuit. When the system is running on battery power, the clock generator will generate a low-frequency clock signal to minimize power consumption of the load circuit.
FIG. 4 illustrates frequency selection as is commonly practiced. In general, the lower the actual temperature of the chip, the faster it can be clocked. In general, higher operating voltages will enable faster clocking. In the example shown, the chip can receive any of four different voltage levels, from a low of V1 to a high of V4. The chip can be subjected to a range of temperatures below a maximum temperature (Tjmax) at which the device ceases to operate correctly or may even suffer permanent damage. The maximum operating temperature is generally specified at some lower temperature Ttest, to provide a safety margin against such occurrences. In selecting a maximum specified operating frequency Flimit for the chip, the manufacturer typically will simply use the worst corner case (WC) of Ttest and V1, which combination dictates the Flimit frequency.
At any temperature below Ttest, the chip will be operated at Flimit. If the temperature manages to climb above Ttest, the thermal throttling mechanism will cut the frequency to reduce the power consumption of the chip, and thereby reduce the temperature of the chip. The thermal throttling mechanism drives the frequency to zero before Tjmax is reached, to prevent catastrophic failure of the chip. In the more recent technologies, the thermal throttling mechanism may also be reducing the voltage in order to reduce power consumption, and may ultimately take the voltage to zero as the temperature approaches Tjmax.
It can be seen that the prior art operates the chip in what may be termed an “actual operating range” (AOR) which is the area under the heavy frequency line, and that the prior art does not take advantage of the additional “valid operating range” (VOR) which lies above that line and below a respective supply voltage line V1-V4. Typically, the part will be operated on the heavy frequency line. Thus, because the prior art has limited the operating frequency based upon a worst corner case assumption about voltage and temperature, and because these conditions will not typically be present (individually, much less in combination), the prior art leaves a great deal of available performance on the table.
What is needed, then, is an improvement in the art which allows the chip to operate in this valid operating range when operating conditions permit.